1. Field of the Invention
The present invention relates generally to semiconductor memory devices and operation executing system using the same. More particularly, the present invention relates to an improvement of operation mode for such a dynamic random access memory as having a execution block contained in one chip.
2. Description of the Background Art
For example, numbers of dynamic RAMs are used in an image processing apparatus, wherein writing and reading of image data of the dynamic RAM is controlled by a CPU. However, since operation processing in a chip is more likely to reduce a processing speed required for processing some image, an integrated circuit containing a dynamic RAM and an operation execution block in one chip has been put into practical use.
FIG. 13 is a schematic block diagram of such integrated circuit. Referring to FIG. 13, memory cell arrays 1-4 have memory capacity of 512 rows and 512 columns corresponding to data input/output terminals DO1-D04. Each of the memory cell arrays 1-4 has a row decoder 5, a column decoder 6 and an I/O gate 7 provided therein. Address input terminals A0-A8 receive row address (X) signals and column address (Y) signals as external address signals and also receive operation command CMD in a time divisional multiplexed manner, and then the external address signals are latched in an address buffer 9. Since address is a kind of command and different from data, the operation command CMD is input to the address input terminals A0-A8 but not to the data input/output terminals D01-D04. The row address signals latched in the address buffer 9 are applied to the row decoders 5 wherein one row is selected among 512 rows of each of the memory cell arrays 1-4, while the column address signals are applied to the column decoders 6 wherein one column is selected among the 512 columns in the memory cell array 1. Read data Mi of the selected address is applied to a operation execution block 8 through the I/O gate 7.
The above-described operation command CMD latched in the address buffer 9 is latched in a CMD buffer 10 and then applied to the operation block 8. The input/output terminals DO1-DO4 receive input data Di, the input data Di is latched in an input buffer 12 at each timing of signals, RAS, CAS, WB/WE and DT/OE input to control input terminals and then the latched input Di is applied to the operation block 8. The operation block 8 executes operations of the read date Mi and the input data Di latched in the input buffer 12 at the operation command CMD latched in the CMD buffer 10 and data Wi which are results of the executed operations are written in the memory cell arrays 1-4.
FIG. 14 is a diagram explaining a outline of an operation processing by the operation execution block in FIG. 13, FIG. 15 is a table showing the operation contents executed in the operation execution block and FIG. 16 is a timing chart showing operation processing cycles of a conventional semiconductor memory device.
Now, referring to FIG. 13-FIG. 16, operation of the conventional semiconductor memory device will be described. As shown in FIG. 16, in the first half of the operation command setting cycle, the operation command CMD is latched in the address buffer 9 and in the latter half of the operation executing cycle, an operation processing is performed in accordance with the latched operation command CMD, so that the data Wi of the result thereof is written in the memory cell arrays 1-4. Namely, when the row address strobe signal RAS attains the "L" (logical low) level, the column address strobe signal CAS attains the "L" level, the output enable signals DT/OE attains a "H" (logical high) level and the write enable signal WB/WE attains the "L" level, so that the operation command CMD is applied to the address input terminals A0-A8, the operation command CMD is latched in the CMD buffer 10 through the address buffer 9. At this time, write mask data is applied to the data input/output terminals DO1-DO4.
After the operation command is latched in the CMD buffer 10, the operation is executed in the latter half of the operation cycle as shown in FIG. 16. Namely, a predetermined address of each of the memory cell arrays 1-4 is specified by the row address strobe signal RAS and the column address strobe signal CAS, so that the read data Mi is applied to the operation block 8, and the write enable signal WB/WE attains the "L" level, so that the input data Di input to the data input/output terminals DO1-DO4 is latched in the input buffer 12 and then applied to the operation block 8, whereby the operation is executed in accordance with the operation command CMD. As shown in FIG. 13, the operation command CMD comprises 4 bits (A0-A3) and an AND operation and an OR operation between the read data Mi and the input data Di are executed based on whether the bit is "0" or "1".
As described above, in the conventional semiconductor memory device, the operation command CMD is latched in the CMD buffer 10 in the first half of the operation command setting cycle and the operation block 8 executes the operation of the input data Di and the read data Mi in accordance with the operation command CMD in the latter half of the operation executing cycle, which makes neither setting nor execution of the operation command CMD in the same cycle possible, resulting in a longer processing time period.